This invention relates to programmable digital data processors, and more particularly to a sequence control unit (CU) for an arithmetic unit (AU) which permits optimum overlapping of the execution of instructions.
In many applications it is necessary to process large quantities of iterative data (blocks or arrays) in a predetermined manner in real time. If the data are continually changing, such as in the processing of radar or sonar signals, the finite time required to process the data becomes significant. That is particularly true in modern systems having large arrays of data to be processed.
Within the last few years, the design of digital signal processors has undergone major transitions. The first digital signal processors were dynamically structurable under the supervision of a general purpose computer or a special purpose signal processor controller. The signal processors, however, were special purpose in nature and not readily adaptable to a wide variety of applications.
The next step in the development of digital signal processors, made possible by advances in integrated circuit technology, was the design of signal processors which could be programmed directly. These programmable signal processors were characterized by multiple memories, powerful arithmetic units, and pipelined instruction streams with conventional instruction decoding. The limitation on these processors was the inflexibility of their instruction sets. The instruction requirements for different signal processing applications are almost always different. For example, one application may require a very efficient complex multiplication while another requires a very efficient way of developing a "dot product". This leads to the design of programmable signal processors especially adapted to different applications.
For real time signal processor applications, it is necessary to have efficient instruction sets so that the processing can be completed in real time. However, even efficient instruction sets will not yield the optimum in speed of processing. For the optimum, it would be necessary to have not only pipelined instruction streams, but to also have execution of the instructions in the pipeline overlapping so that execution of more than one instruction is in progress simultaneously, and ideally to have the execution of one instruction completed every clock cycle such that, once the instruction pipeline is filled, there is an instruction completed every clock cycle. In the past, the instruction sequence control unit has merely permitted another instruction to be fetched and decoded while the current instruction is being executed.